1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to output buffers for semiconductor devices and related methods.
2. Description of the Related Art
A semiconductor device may use a buffer circuit to drive relatively high current loads. In particular, a circuit which drives an output pin on which a relatively high current load is weighed may be referred to as an output buffer circuit. FIG. 1 is a circuit diagram of a conventional output buffer circuit which receives a control signal CNT, and FIG. 2 is a circuit diagram of a conventional output buffer which receives two control signals CNT1 and CNT2. The conventional output buffer circuits shown in FIGS. 1 and 2 include a pull-up transistor 11, a pull-down transistor 13, a NAND gate 15 (or 25) which drives the pull-up transistor 11, and a NOR gate 17 (or 27) which drives the pull-down transistor 13, respectively.
In the case of a conventional output buffer circuit, it may be important to maintain characteristics of the NAND gate 15 (or 25) as equivalent to those of the NOR gate 17 (or 27) to reduce an occurrence of a high/low skew of data output via an output pin DQ. Such a conventional output buffer circuit may be designed in which sizes of transistors are adjusted so that the NAND gate 15 (or 25) has characteristics approximately the same as the NOR gate 17 (or 27). Nonetheless, characteristics of the NAND gate 15 (or 25) may be different from those of the NOR gate 17 (or 27) if there are changes in process, voltage, and/or temperature (PVT).
Moreover, when data is divided into some parts and input to the NAND gate 15 (or 25) and the NOR gate 17 (or 27), differences between input capacitances of the NAND gate 15 (or 25) and the NOR gate 17 (or 27) may become relatively large and thus characteristics of the NAND gate may be significantly different from characteristics of the NOR gate due to changes in PVT. A skew of data output via the output pin DQ may thus increase.